D latch

module dlatch(d,clk,q);
input d,clk;
output q;
reg op;

assign q=op;

always @(clk,d)
begin
if(clk)
  op<=d;
else
  op<=op;
end
endmodule
//************************************
module dlatch_tb();
reg d,clk;
wire q;

dlatch mut(d,clk,q);

initial
begin
clk=0;
d=0;
#2 d=1;
#4 d=0;
#7 d=1;
end
always #5 clk=~clk;

endmodule