4 bit wallace tree multiplier :

module wallace(x,y,z);

input [3:0]x,y;
output [7:0]z;
wire [15:0]a;
wire sum1,sum2,sum3,cout1,cout2,cout3;
wire s1,s2,s3;
wire c1,c2,c3,c4,c5,c6,c7,c8;

and(a[0],x[0],y[0]);
and(a[1],x[0],y[1]);
and(a[2],x[0],y[2]);
and(a[3],x[0],y[3]);
and(a[4],x[1],y[0]);
and(a[5],x[1],y[1]);
and(a[6],x[1],y[2]);
and(a[7],x[1],y[3]);
and(a[8],x[2],y[0]);
and(a[9],x[2],y[1]);
and(a[10],x[2],y[2]);
and(a[11],x[2],y[3]);
and(a[12],x[3],y[0]);
and(a[13],x[3],y[1]);
and(a[14],x[3],y[2]);
and(a[15],x[3],y[3]);

// level 1
half_adder ha1(s1,c1,a[6],a[3]);
half_adder ha2(s2,c2,a[10],a[7]);

// level 2
full_adder fa1(sum1,cout1,a[12],a[9],s1);
full_adder fa2(sum2,cout2,a[13],s2,c1);
full_adder fa3(sum3,cout3,a[11],a[14],c2);
half_adder ha3(s3,c3,a[5],a[2]);

//level 3
assign z[0]=a[0];
half_adder ha4(z[1],c4,a[1],a[4]);

full_adder fa4(z[2],cout4,a[8],s3,c4);
full_adder fa5(z[3],cout5,sum1,c3,cout4);
full_adder fa6(z[4],cout6,cout1,sum2,cout5);
full_adder fa7(z[5],cout7,cout2,sum3,cout6);
full_adder fa8(z[6],z[7],cout3,a[15],cout7);
     
endmodule

//*************************

module full_adder(sum,cout,a,b,cin);

input a,b,cin;
output sum,cout;
wire s,c1,c2;

half_adder hf1(s,c1,a,b);
half_adder hf2(sum,c2,s,cin);
or(cout,c1,c2);

endmodule

//*************************


module half_adder(s,c,a,b);

input a,b;
output s,c;

assign s=(a^b);
assign c=(a & b);

endmodule

// test bench

module test_wallace();
reg [3:0]a;
reg [3:0]b;
wire [7:0]result;

initial begin
a=15;           // all partial products are 1 and output is 11100001
b=15;
end

wallace mut(a,b,result);
endmodule