Verilog program for basic binary multiplier :

module binary_multiplication(i1,i2,op);

input [2:0]i1,i2;
output reg [5:0]op;  // number of bits of output is sum of number of bits of both inputs

integer i;
//reg [5:0]temp;

always @(i1 or i2)
begin
  op=0;
  for(i=0;i<=2;i=i+1) 
    begin
      if(i2[i]==0)
        op=op;
      else
        op=op + (i1<<i);
    end     
end
endmodule

Test bench :

module test_multiplication();
 
reg [2:0]i1,i2;
wire [5:0]op;

initial begin
 
# 10 i1=3'b101;
i2=3'b011; 
end

binary_multiplication xx(i1,i2,op);

endmodule