VHDL Program for Counter

 VHDL MODULE FOR COUNTER :

entity cou is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           qout : out  STD_LOGIC_VECTOR(2 DOWNTO 0));
end cou;

architecture Behavioral of cou is
signal count : STD_LOGIC_VECTOR(2 DOWNTO 0) ;

begin

process(clk,rst)
begin


if rst='1' then
count<="000";

elsif(clk 'event and clk='1') then

count<=count+1;

end if;

end process;
qout<=count;


end Behavioral;

TEST BENCH :

BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut: cou PORT MAP(
        clk => clk,
        rst => rst,
        qout => qout
    );

    tb : PROCESS
    BEGIN
   
clk<='0';
wait for 10 ns;
clk<='1';
wait for 10 ns;
end process;

process
begin
rst <='1';
wait for 10 ns;
rst <='0';
wait for 150 ns;

       
END PROCESS;

END;

OUTPUT :